CPU Silicon Security Research and Fuzzing (RISC-V)

I’ve embarked on a brief journey to learn RISC-V and I ended up finding a niche of interesting material on security research on fuzzing, so I pivoted my attention to that. Here’s a brief summary of what I found.

So far, I’ve been reading the following books.

• The RISC-V Reader: An Open Architecture Atlas (2017) by David Patterson (RISC-V Foundation, Google, Berkeley), Andrew Waterman (SiFive). This is a relatively brief but dense introduction to the ISA, with a nicely organized visual representation of all instructions in just half a page! You’ll learn the details of how instructions are encoded and admire the beauty of such a well-thought design.
• RISC-V Assembly Language Programming: using ESP32-C3 and QEMU (2022) by Warren Gay is a hands-on, slow-paced, journey of the RV32/64 instructions through examples that you can run immediately on your computer (QEMU) or on real RICV-V silicon (ESP32-C3).

How Popular is RISC-V as a Platform CPU?

Many hardware peripheral manufacturers use RISC-V blocks to make custom, powerful, and flexible management co-processors to run control firmware to manage the peripheral (e.g., GPUs). NVIDIA is integrating the open-standard RISC-V architecture into its products, initially using it for internal microcontrollers and more recently extending it to be a primary application processor by making its CUDA platform compatible with RISC-V CPUs.

RISC-V Cloud Offerings

However, RISC-V hasn’t yet reached a point where it may be a viable aleternative to, say, Intel, AMD, or ARM-based platform CPUs. However, we see some products and services at the horizon. To date, the following cloud providers offer RISC-V computing services.

RISC-V Implementations

Needless to say, there are countless RISC-V boards. I stopped listing them when I realized there are quite some comprehensive lists around. Anyway, here’s my summary table based on the most comprehensive and maintained lists of RISC-V implementations:

• Alex Bradbury compiled a list of commercially available RISC-V silicons (last updated 2023-03-31).
• Aleksander Krimsky maintains a list of all commercially available RISC-V single-board computers (last updated 2024-05-01).
• RISC-V Wikipedia page (last updated 2024-05-24).
• RISC FIVE forum (last updated: 2023-03-09).

The list does not contain boards where the RISC-V block is not the main core (e.g., coprocessors).

Fuzzing Hardware Like Software

From a security standpoint, what makes RISC-V interesting is that the hardware definition of some IP cores is open source, which means that it can be formally verified and, best of all, fuzzed. Like software! The idea is “simple”:

• compile the core into an executable format,
• shovel it into a simulator,
• randomize inputs (i.e., instructions and data),
• observe execution,
• measure coverage,
• repeat,
• …wait, what now?

The design and implementation of such a fuzzer are quite challenging, mainly because, unlike with a traditional software program, it’s difficult to define an oracle that tells us when a bug in a CPU design has been found, because a CPU just…interprets instructions based on state and data. It can’t “crash”. And if we observe a crash, most likely it’s the simulator crashing. We don’t yet have a precise way to tell whether the CPU being simulated and fuzzed is behaving according to the specs, or maybe according to the best golden model we have so far. Even in this case, is the golden model representative? What are we trying to compare against? We don’t (yet!) have the choice of memory or address sanitizers like we have for fuzzers. In other words, there’s a huge body of research, development, and hacking waiting to be unfolded. There exist the notion of coverage, which is good news.

RISC-V Fuzzing Experiments and Tools

Papers with Tools

I selected the following papers because (1) the evaluation is done on RISC-V cores or a full processor, and (2) they come with code, so the results are reproducible. In some cases, they’re used to continuously fuzz the RTL of the cores, like in the case of the work by Trippel et al., which, according to the authors (and this repository), their tool is used to fuzz Google’s OpenTitan.

• Fabian et al., RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing
  • Tool: RISCVuzz
  • Target RISC-V:
    • C910 (TH1520 SoC)
• Solt et al., Cascade: CPU Fuzzing via Intricate Program Generation, USENIX Security, 2024.
  • Tool: Cascade (Docker)
  • Target RISC-V:
    • VexRiscv (SpinalHDL)
    • PicoRV32 (Verilog)
    • Kronos (Verilog)
    • CVA6 (Verilog)
    • BOOM (Chisel)
• Canakci et al., ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance, IEEE HOST, 2023.
  • Tool: ProcessorFuzz (Docker)
  • Target RISC-V:
    • BOOM (Chisel)
    • BlackParrot (Verilog)
    • Rocket (Verilog)
• Trippel et al., Fuzzing Hardware Like Software, USENIX Security, 2022.
  • Tool: googleintern/hw-fuzzing (Docker)
  • Target RISC-V:
    • OpenTitan (AES, HMAC, KMAC, Timer)
• Hur et al., DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs, IEEE S&P, 2021.
  • Tool: DifuzzRTL
  • Target RISC-V:
    • BOOM (Chisel)
    • mor1kx (Verilog)
    • Rocket (Verilog)
• Laeufer et al., RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs, IEEE/ACM ICCAD, 2018.
  • Tool: RFUZZ (VM)
  • Target RISC-V:
    • Rocket (Verilog)
    • Sodor (Chisel)

Known Vulnerabilities in RISC-V Designs

Credits

Photo of the ESP32-C2 die: ESP32-C2 and Why It Matter-s